从画时序图开始的二进制灯
#申请原创# #每日话题# #有奖活动#@21小跑堂首先得掌握流水灯计数器从第一节直接挪用多加一个归零判断module binary_led(
input clk,
input reset_n,
output reg led
);
parameter MAX_COUNT_S = 'd49_999_999;//一秒
reg counter_delay_s;
reg count3_0;
//HS秒
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
counter_delay_s <= 'd0;
else if(counter_delay_s == MAX_COUNT_S)
counter_delay_s <= 0;
else
counter_delay_s <= counter_delay_s + 1'b1;
//HS到第4位就回去
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
count3_0 <= 'd0;
else if(count3_0 == 'd4)
count3_0 <= 0;
else if(counter_delay_s == MAX_COUNT_S)
count3_0 <= count3_0 + 1'd1;
//HS呼吸灯
always @(posedge clk or negedge reset_n)
if(!reset_n)
led <= 0;
else case (count3_0)
0 : led <= 4'b0001;
1 : led <= 4'b0010;
2 : led <= 4'b0100;
3 : led <= 4'b1000;
default: led <= led;
endcase
endmodule下来是仿真
module binary_led_tb;
reg clk = 0 ;
reg reset_n = 0 ;
// led Outputs
wireled ;
parameter MAX_COUNT_S= 'd49_999_999;
initial clk = 1;
always #10 clk = ~clk;
binary_led #(
.MAX_COUNT_S ( 49_99 ))
u_led (
.clk ( clk ),
.reset_n ( reset_n ),
.led ( led )
);
initial begin
reset_n = 0;
#201;
reset_n = 1;
#40000000;
$stop;
$finish;
end
endmodule时序图
以下为二进制流水灯
module binary_led(
input clk,
input reset_n,
output reg led
);
parameter MAX_COUNT_S = 'd49_999_999;//一秒
reg counter_delay_s;
reg count3_0;
//HS秒
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
counter_delay_s <= 'd0;
else if(counter_delay_s == MAX_COUNT_S)
counter_delay_s <= 0;
else
counter_delay_s <= counter_delay_s + 1'b1;
//HS到第4位就回去
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
count3_0 <= 'd0;
else if(count3_0 == 'd15)
count3_0 <= 0;
else if(counter_delay_s == MAX_COUNT_S)
count3_0 <= count3_0 + 1'd1;
//HS呼吸灯
// always @(posedge clk or negedge reset_n)
// if(!reset_n)
// led <= 0;
// else case (count3_0)
// 0 : led <= 4'b0001;
// 1 : led <= 4'b0010;
// 2 : led <= 4'b0100;
// 3 : led <= 4'b1000;
// default: led <= led;
// endcase
// HS二进制灯
always @(posedge clk or negedge reset_n)
if(!reset_n)
led <= 0;
else case (count3_0)
0 : led <= 4'b0001;
1 : led <= 4'b0010;
2 : led <= 4'b0011;
3 : led <= 4'b0100;
4 : led <= 4'b0101;
5 : led <= 4'b0110;
6 : led <= 4'b0111;
7 : led <= 4'b1000;
8 : led <= 4'b1001;
9 : led <= 4'b1010;
10 : led <= 4'b1011;
11 : led <= 4'b1100;
12 : led <= 4'b1101;
13 : led <= 4'b1110;
14 : led <= 4'b1111;
default: led <= led;
endcase
endmodule结果
可以不使用仿真直接烧录，xdc匹配到对应的管脚即可
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