GD32H759 UART DMA接收问题

ryan_jiang 发表于 2025-4-23 14:32

GD32H759 UART开启DMA接收+空闲中断；开启了cache。第一次接收的数据是正确的，后面接收的数据，只要接收的数据长度大于上一次接收的数据才能正确接收；小于上一次的长度，接收不到数据，DMA读取的数据长度和数据还是保持上次的数据，没有更新，但是回正常进入空闲中断，读取DMA的接收数据长度还是上次的。比如第一次发送数据123456789这9个数据是正常接收的；后面我发送123456789abc,这样也是正常接收的；但是我发qwe这三个数据，会正常进入空闲中断，但是读取DMA接收数据长度还是上次123456789abc的数据长度，缓存的数据也是上次的123456789abc。很奇怪，不知道问题出在哪？
#define USART1_RDATA_ADDRESS    (&USART_RDATA(USART1))
#define USART1_TDATA_ADDRESS    (&USART_TDATA(USART1))

#define UART1_BUADRATE 115200

//Uart1_Com_TypeUart1_Com={0};

__attribute__ ((aligned(32))) uint8_t uart1_tx_buf;
__attribute__ ((aligned(32))) uint8_t uart1_rx_buf;
uint8_t TransmitDone = 0;
void gd32h7_uart1_config(void)
{
/* enable GPIO clock */
rcu_periph_clock_enable(RCU_GPIOA);
/* enable USART clock */
rcu_periph_clock_enable(RCU_USART1);
/* connect port to USART TX */
gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_2);
/* connect port to USART RX */
gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_3);
/* configure USART TX as alternate function push-pull */
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_2);
/* configure USART RX as alternate function push-pull */
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_3);
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_3);

nvic_irq_enable(USART1_IRQn, 1, 0);
/* USART configure */
usart_deinit(USART1);
usart_oversample_config(USART1,USART_OVSMOD_16);
usart_word_length_set(USART1,USART_WL_8BIT);
usart_parity_config(USART1,USART_PM_NONE);
usart_sample_bit_config(USART1,USART_OSB_1BIT);
usart_baudrate_set(USART1, UART1_BUADRATE);
usart_receive_config(USART1, USART_RECEIVE_ENABLE);
usart_transmit_config(USART1, USART_TRANSMIT_ENABLE);
usart_dma_receive_config(USART1, USART_RECEIVE_DMA_ENABLE);
usart_dma_transmit_config(USART1, USART_TRANSMIT_DMA_ENABLE);
usart_interrupt_enable(USART1,USART_INT_IDLE);
usart_interrupt_flag_clear(USART1, USART_INT_FLAG_IDLE);
usart_enable(USART1);

}

#ifdef USE_PRINTF
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
usart_data_transmit(USART1, (uint8_t)ch);
while(RESET == usart_flag_get(USART1, USART_FLAG_TBE));

return ch;
}
#endif
void gd32h7_uart1_dma_config(void)
{
dma_single_data_parameter_struct dma_init_struct;
/* enable DMA clock */
rcu_periph_clock_enable(RCU_DMA1);
/* enable DMAMUX clock */
rcu_periph_clock_enable(RCU_DMAMUX);
#ifndef USE_PRINTF
/* initialize the com */
nvic_irq_enable(DMA1_Channel0_IRQn, 5, 0);

/* initialize DMA channel 0 --> UART1_TX*/
dma_deinit(DMA1, DMA_CH0);
dma_single_data_para_struct_init(&dma_init_struct);
dma_init_struct.request    = DMA_REQUEST_USART1_TX;
dma_init_struct.direction = DMA_MEMORY_TO_PERIPH;
// dma_init_struct.memory0_addr= (uint32_t)txbuffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
// dma_init_struct.number    = ARRAYNUM(txbuffer);
dma_init_struct.periph_addr= (uint32_t)USART1_TDATA_ADDRESS;
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_single_data_mode_init(DMA1, DMA_CH0, &dma_init_struct);

/* configure DMA mode */
dma_circulation_disable(DMA1, DMA_CH0);
/* USART DMA enable for transmission and reception */
usart_dma_transmit_config(USART1, USART_TRANSMIT_DMA_ENABLE);
/* enable DMA channel 0 transfer complete interrupt */
dma_interrupt_enable(DMA1, DMA_CH0, DMA_CHXCTL_FTFIE);
/* enable DMA channel 0 */
// dma_channel_enable(DMA1, DMA_CH0);
#endif
/* initialize DMA channel 1 --> UART1_RX*/
dma_deinit(DMA1, DMA_CH1);
dma_single_data_para_struct_init(&dma_init_struct);
dma_init_struct.request    = DMA_REQUEST_USART1_RX;
dma_init_struct.direction = DMA_PERIPH_TO_MEMORY;
// dma_init_struct.memory0_addr= (uint32_t)rxbuffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
// dma_init_struct.number    = 32;
dma_init_struct.periph_addr= (uint32_t)USART1_RDATA_ADDRESS;
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_single_data_mode_init(DMA1, DMA_CH1, &dma_init_struct);

/* configure DMA mode */
dma_circulation_disable(DMA1, DMA_CH1);
/* USART DMA enable for reception */
usart_dma_receive_config(USART1, USART_RECEIVE_DMA_ENABLE);
/* disable DMA channel 1 transfer complete interrupt */
dma_interrupt_disable(DMA1, DMA_CH1, DMA_CHXCTL_FTFIE);
/* enable DMA channel 1 */
// dma_channel_enable(DMA1, DMA_CH1);
}

void bspUsart1_DMA_Transmit(uint8_t *txd, uint32_t Size)
{
dma_channel_disable(DMA1, DMA_CH0);
dma_memory_address_config(DMA1,DMA_CH0,DMA_MEMORY_0,(uint32_t)txd);
dma_transfer_number_config(DMA1,DMA_CH0,Size);
usart_dma_transmit_config(USART1, USART_TRANSMIT_DMA_ENABLE);
dma_channel_enable(DMA1, DMA_CH0);

}

void bspUsart1_DMA_Receive(uint8_t *rxd, uint32_t Size)
{
dma_channel_disable(DMA1, DMA_CH1);
dma_memory_address_config(DMA1,DMA_CH1,DMA_MEMORY_0,(uint32_t)rxd);
dma_transfer_number_config(DMA1,DMA_CH1,Size);
usart_dma_receive_config(USART1, USART_RECEIVE_DMA_ENABLE);
dma_channel_enable(DMA1, DMA_CH1);
}

void bsp_uart_init(void)
{
gd32h7_uart1_dma_config();
gd32h7_uart1_config();
bspUsart1_DMA_Receive(uart1_rx_buf,UART1_RECV_SIZE);
}

/*!
\brief    this function handles USART interrupt exception
\paramnone
\param none
\retval none
*/

void USART1_IRQHandler(void)
{
uint16_t recv_len=0;

if(RESET != usart_interrupt_flag_get(USART1, USART_INT_FLAG_IDLE))
{
   usart_interrupt_flag_clear(USART1, USART_INT_FLAG_IDLE);

dma_channel_disable(DMA1, DMA_CH1);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FTF);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_HTF);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_TAE);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FEE);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FEE);
SCB_InvalidateDCache_by_Addr(uart1_rx_buf,UART1_RECV_SIZE);
   /* number of data received */
   recv_len = UART1_RECV_SIZE - (dma_transfer_number_get(DMA1, DMA_CH1));

}
}

/*!
\brief    this function handles DMA_Channel0_IRQHandler exception
\paramnone
\param none
\retval none
*/
void DMA1_Channel0_IRQHandler(void)
{
if(RESET != dma_interrupt_flag_get(DMA1, DMA_CH0, DMA_INT_FLAG_FTF))
{
   dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_FTF);
dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_HTF);
dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_TAE);
dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_FEE);
dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_FEE);
TransmitDone = 1;

}
}

/*!
\brief    this function handles DMA_Channel1_IRQHandler exception
\paramnone
\param none
\retval none
*/
void DMA1_Channel1_IRQHandler(void)
{
if(RESET != dma_interrupt_flag_get(DMA1, DMA_CH1, DMA_INT_FLAG_FTF))
{
   dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FTF);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_HTF);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_TAE);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FEE);
dma_interrupt_flag_clear(DMA1, DMA_CH1, DMA_INT_FLAG_FEE);

}
}

classroom 发表于 2025-4-24 10:54

DMA缓存未正确更新？GD32H759启用了Cache，而DMA直接访问内存。若未正确处理Cache一致性，可能导致DMA读取到的是缓存中的旧数据，而非内存中的最新数据。

fxyc87 发表于 2025-4-24 11:47

arm cortex m7有一个概念叫缓存，如果你不懂，你可以将其禁用掉。牺牲一点性能。

flycamelaaa 发表于 2025-4-24 12:00

DMA的传输长度可能未正确重置或更新，导致DMA始终按照上一次的配置进行传输。

powerantone 发表于 2025-4-24 13:20

若未正确重置DMA传输长度，DMA可能继续使用旧长度，导致数据截断或错误。

stormwind123 发表于 2025-4-24 14:04

接收缓冲区未正确对齐？

probedog 发表于 2025-4-24 15:00

空闲中断处理函数中，可能未正确读取DMA传输的数据长度或未更新接收状态。

classroom 发表于 2025-4-24 16:23

问题应该主要由Cache一致性和DMA配置不当引起。

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GD32H759 UART DMA接收问题