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Synplify pro综合教程
2019-10-8 09:43
- FPGA论坛
- 20
- 3566
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基于Xilinx PCIe Core 的DMA设计
2013-2-11 15:09
- FPGA论坛
- 19
- 2893
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复位诀窍: 考虑局部而非全局
2012-7-17 15:42
- FPGA论坛
- 17
- 1789
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基于Xilinx+VirtexⅡ+Pro的过程级动态部分可重构系统设计与实现
2019-11-7 11:26
- FPGA论坛
- 8
- 1345
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生成的ip核如何编写驱动函数,怎样使用?
2012-7-9 20:58
- FPGA论坛
- 8
- 2159
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急!用VHDL做PCI管理编程
2012-7-9 21:38
- FPGA论坛
- 33
- 3909
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用CORE Generator产生PCIe Endpoint时到33%停止不动
2012-7-9 21:37
- FPGA论坛
- 4
- 1761
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EDK官方实验
2012-7-9 21:39
- FPGA论坛
- 7
- 1537
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请问fpga设计的串口一定时间后输出全是0的原因
2012-7-16 21:01
- FPGA论坛
- 9
- 1356
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