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语法错误A begin/end block was found with an empty body.
2017-12-17 11:28
- FPGA论坛
- 2
- 4671
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Verilog串口通信问题
2017-12-17 11:24
- FPGA论坛
- 6
- 1764
![](https://bbs.21ic.com/static/image/common/icon_quote_m_s.gif)
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请教Verilog中case书写用法
2017-12-17 11:19
- FPGA论坛
- 2
- 1845
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同段代码 在 test bench和在工程模块中结果不一样
2017-12-17 11:17
- FPGA论坛
- 2
- 1098
![](https://bbs.21ic.com/static/image/common/icon_quote_m_s.gif)
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哪位大神帮忙看一下Verilog程序,是哪里的问题
2017-12-17 11:11
- FPGA论坛
- 6
- 1133
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我的 VGA 模块来了,含视频教程。大家看看
2020-1-2 23:03
- FPGA论坛
- 93
- 10618
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勇敢的芯伴你玩转Altera FPGA连载28: 内里本质探索——器件...
2017-12-12 15:39
- FPGA论坛
- 1
- 661
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FPGA做的OV7670的图像显示(EDK方式实现),小玩意儿
2018-3-8 16:02
- FPGA论坛
- 11
- 2319
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verilog 写的串口 在一个状态机里面,有一个寄存器无法执...
2017-12-10 22:35
- FPGA论坛
- 14
- 1794
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testbench的设置问题
2017-12-10 21:53
- FPGA论坛
- 4
- 954
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【锆石科技】关于 Verilog HDL 语言的一些关键问题解惑
2024-2-6 19:21
- FPGA论坛
- 530
- 49700
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刚学Verilog,编了下面的程序,仿真时运行出不来结果
2017-12-17 11:07
- FPGA论坛
- 1
- 1313
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初学Verilog,出现的错误解决不了,求帮忙
2017-12-17 11:09
- FPGA论坛
- 5
- 9416
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quartus RTL仿真和门极仿真结果不一样怎么处理
2017-12-17 11:30
- FPGA论坛
- 4
- 2212
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