从画时序图开始的计数器
本帖最后由 不是张角 于 2025-3-6 17:20 编辑#有奖活动# #申请原创#@21小跑堂 https://cdn.nlark.com/yuque/0/2024/png/42990414/1722223582571-7fd3c3f7-be07-40bc-9350-8a1168cd7295.pnghttps://cdn.nlark.com/yuque/0/2024/png/42990414/1722221817067-2c5b9522-05d1-4504-9dc1-957bdd833af1.png该图是通过timegen3所画
module counter(
input clk,
input reset_n,
output reg out
);
always @(posedge clk or negedge reset_n)
if(!reset_n)
out <= 0;
else
out <= 1;
endmodulehttps://cdn.nlark.com/yuque/0/2024/png/42990414/1722226454447-706230af-0b1e-4a68-80df-c648f28a13e5.png这句的意思就是每当时钟上升或者复位就进入看图可以知道在第二个始终上升沿reset_n上拉,但是此时他还是0,所以到下一个时钟上升沿out就会为1
module counter_tb;
reg clk;
reg reset_n;
wire out;
counter counter_tb0(
.clk(clk),
.reset_n(reset_n),
.out(out)
);
initial clk = 1;
always #10 clk = ~clk;
initial begin
reset_n = 0;
#201;
reset_n = 1;
#40000000;
$stop;
end
endmodule下来就要考虑计数器的情况:得到的时序图和自己需要得到的一致
https://cdn.nlark.com/yuque/0/2024/png/42990414/1722228692387-9ac70407-d1b7-40f3-88c2-35b4a90eeece.pngparameter MAX_COUNT_S = 'd49_999_999;//一秒
parameter MAX_COUNT_M = 'd59;//一分钟
reg counter_delay_s;
reg counter_delay_m;//分钟
//HS秒
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
counter_delay_s <= 'd0;
else if(counter_delay_s == MAX_COUNT_S)
counter_delay_s <= 0;
else
counter_delay_s <= counter_delay_s + 1'b1;
//HS分
always @(posedge clk or negedge reset_n) //表示只要是始终上升沿或复位下降沿都会运行
if(!reset_n)
counter_delay_m <= 'd0;
else if(counter_delay_s == MAX_COUNT_S && counter_delay_m == MAX_COUNT_M)//当一分钟时候
counter_delay_m <= 0;
else if(counter_delay_s == MAX_COUNT_S)
counter_delay_m <= counter_delay_m + 1'b1;
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