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Agenda (CST)
Click on the speaker link for additional information
14.00 Arrival and Networking
14.10 Welcome
14.15 Test and Verification Solutions, Mike Bartley (CEO and Founder)
Title: Improving Debug - Our biggest challenge?
Presentation will be made in English
14.25 Real Intent, Ramesh Dewangan (Vice President)
Title: Shortening Debug with New Methods in Static Verification
Presentation will be made in English
14.55 Solvertec GmbH, Daniel Große (CEO)
Title: Circuit Design: Slip Schedule or Automate Debug
Presentation will be made in English
15.25 Mentor Graphics, Albert Chiang (Product Marketing Manager)
Title: Introducing Mentor Visualizer - A Powerful Debug Environment for Complex SOCs
Presentation will be made in Chinese
15.55 Coffee Break (5 minutes)
16.00 Cadence, Chen Liang (Principal Solutions Engineer)
Title: Revolutionary Debug Techniques to Improve Verification Productivity
Presentation will be made in Chinese
16.30 Synopsys, Rich Chang (Product Marketing Manager)
Title: Complete SoC Debug Solution – From HW to SW debugging approaches.
Presentation will be made in Chinese
17.00 ARM, Haiyan Zhao (Senior Applications Engineer)
Title: The usage of Coresign for debug/trace on a real platform
Presentation will be made in Chinese
17.30 Local Q&A Session (5 minutes)
17.35 Close and Networking
Agenda Subject to Change
Why not visit our website?
Chinese Version
http://www.dvclub.org.cn/ or http://dvclub.org.cn/
English Version
http://www.dvclub.org.cn/drupal/en
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Visit and join the DVClub Shanghai LinkedIn group to keep up to date
About the DVClub Shanghai and the events:
About the initiators:
Mike Bartley is the founder and CEO of Test and Verification Solutions in UK.
Roman Wang is the verification specialist in AMD Shanghai group.
Charles Sun is the VP of TopBrain Design Systems.