Cadence ahdlLib里自带的opamp VerilogA model带宽有限且收敛性差，好不容易找到一个收敛性好的通用VerilogA model.

`include "discipline.h"
`include "constants.h"

`define PI 3.14159265358979

//opamp
//vin_p,vin_n: differential input voltage
//vout: output voltage
//vref: reference voltage
//vdd: positive supply voltage
//vss:  negative supply voltage
//parameters
//gain: open loop gain
//freq_unitygain:gain bandwidth product
//rin: input resistance
//vos_in: input offset voltage
//ibias: input bias current
//ios: input offset current
//iin_max: maximum current
//slewrate: slew rate
//rout: output resistance
//vsoft: soft output limiting value

module opamp(vout, vref, vin_p, vin_n,  vdd, vss);
input vref, vdd, vss;
inout vout, vin_p, vin_n;
electrical vout, vref, vin_p, vin_n, vdd, vss;
parameter real gain=1e8;
parameter real freq_unitygain=1e6;
parameter real rin=1e6;
parameter real vos_in=0;
parameter real ibias=0;
parameter real ios=0;
parameter real iin_max=200e-6;
parameter real slewrate=0.5e-6;
parameter real rout=80;
parameter real vsoft=0.2;

real c1;
real gm;
real r1;
real vmax_in;
real vin_val;
 
electrical cout;

analog begain
  @(initial_step or initial_step("dc")) begin
      c1=iin_max/slewrate;
      gm=2*`PI*freq_unitygain*c1;
      r1=gain/gm;
      vmax_in=iin_max/gm;
   end

   vin_val=V(vin_p,vin_n)+vos_in;
   //input stage
   I(vin_p, vin_n)<+(V(vin_p, vin_n)+vos_in)/rin;
   I(vref, vin_p) <+ (ibias+ios/2);

   I (vref, vin_n) <+ (ibias-ios/2);

  //GM stage with slewing

  I(vref, cout) <+ V(vref, cout)/100e6;

  if (vin_cal > vmax_in)

     I(vref, cout) <+ iin_max;

  else if (vin_cal < -vmax_in)

     I(vref, cout) <+ -iin_max;

 else

     I(vref, cout) <+ gm_nom*vin_val;

 //dominant pole

 I(cout, vref) <+ ddt(c1*V(cout, vref));

 I(cout, vref) <+ V(cout, vref)/r1;

//

//Output Stage

I(vref, vout) <+ V(cout, vref)/rout;

I(vout, vref) <+ V(vout, vref)/rout;

//Soft Output Limiting

if (V(vout) > (V(vsupply_p)-vsoft))

   I(cout, vref) <+ gm_nom* (V(vout, vspply_p)+vsoft);

 else if (V(vout) < (V(vsupply_n)+vsoft))

    I(cout, vref) <+ gm_nom * (V(vout, vspply_n)-vsoft);

end

endmodule

终于写完了，工作太忙