日志
带清零 计数使能和置数的十进制加减计数器
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library ieee;
use ieee.std_logic_1164.all;
entity counter10_updown is
port(clr,ena,clk,updown,load: in std_logic;
d: buffer integer range 0 to 9;
q: buffer integer range 0 to 9;
count:out std_logic);
end entity counter10_updown;
architecture rtl of counter10_updown is
begin
process(clk,clr)
begin
if clr='1' then q<=0;
else
if clk='1' and clk'event then
if load='1' then q<=d;
elsif ena='1'then
if updown='1' then
if q=9 then q<=0;
else
q<=q+1;
end if;
else
if q=0 then q<=9;
else
q<=q-1;
end if;
end if;
end if;
end if;
end if;
if updown='1' then
if q=9 then count<='1';
else count<='0';
end if;
else
if q=0 then
count<='1';
else count<='0';
end if;
end if;
end process;
end architecture rtl;
