问答

[i=s] 本帖最后由 WeToget 于 2021-11-2 18:28 编辑 [/i] Generating "PAR" statistics. INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. Timing Score: 1183542 (Setup: 1183542, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 26.656ns| N/A| 1183536 _BUFGP | HOLD | 0.266ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 2.913ns| N/A| 6 _count | HOLD | 0.508ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net sta | SETUP | N/A| 2.907ns| N/A| 0 te[4]_PWR_35_o_Mux_246_o | HOLD | 0.664ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- 2 constraints not met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. 716 signals are not completely routed. See the Kem_Enc.unroutes file for a list of all unrouted signals. WARNING:Par:100 - Design is not completely routed. There are 716 signals that are not completely routed in this design. See the "Kem_Enc.unroutes" file for a list of all unrouted signals. Check for other warnings in your PAR report that might indicate why these nets are unroutable. These nets can also be evaluated in FPGA Editor by selecting "Unrouted Nets" in the List Window. Total REAL time to PAR completion: 2 hrs 25 mins 47 secs Total CPU time to PAR completion: 2 hrs 25 mins 31 secs Peak Memory Usage: 5232 MB Placer: Placement generated during map. Routing: Completed - errors found. Number of error messages: 0 Number of warning messages: 5 Number of info messages: 2 Writing design to file Kem_Enc.ncd PAR done! Process "Place & Route" failed

[i=s] 本帖最后由 snail180313 于 2021-4-10 10:27 编辑 [/i] 如题，目前在使用已有的项目和板卡进行fpga的入门学习。xilinx芯片，fpga+9054的板卡设计，ise环境。过程中发现verilog中涉及到的输入输出引脚，有一些引脚在.ucf文件中并未进行引脚约束。想询问一下未进行约束的输入输出信号的引脚配置是如何的。引脚电压标准是LVTTL。