modelsim仿真问题赏800家园币

awbl2023-08-27

本帖最后由 awbl 于 2023-8-27 13:33 编辑

在学习FIR的过程中遇到了仿真问题，大家帮忙看一下。1、modelsim版本：modelsim-Altera 10.3d
2、quartus版本：Quartus II 15.0 (64-bit)
3、主程序fir.v:

module fir(
clk ,
rst_n ,
key ,
dac_mode ,
dac_sleep ,
dac_clka ,
dac_dat_a ,
dac_wra ,
dac_clkb ,
dac_dat_b ,
dac_wrb
);
input clk ;
input rst_n ;
input [7:0] key ;
output dac_mode ;
output dac_sleep ;
output dac_clka ;
output [7:0] dac_dat_a ;
output dac_wra ;
output dac_clkb ;
output [7:0] dac_dat_b ;
output dac_wrb ;
//信号类型定义。
reg [7:0] sin_data ;
reg [31:0] cnt1 ;
wire add_cnt1 ;
wire end_cnt1 ;
wire [16:0] addr_temp ;
wire [6:0] addr ;
reg [12:0] x ;
reg [7:0] dac_dat_a ;
wire dac_sleep ;
wire dac_mode ;
wire dac_clka ;
reg [1:0] cnt0 ;
wire add_cnt0 ;
wire end_cnt0 ;
wire [7:0] fir_dout ;
wire fir_dout_vld;
reg [7:0] dac_dat_b ;
wire dac_clkb ;
wire dac_wrb ;
wire [7:0] fir_din ;
wire [7:0] fir_dout2 ;
//设计正弦信号。
always @(*) begin
case(addr)
0: sin_data = 8'h7F;
1: sin_data = 8'h85;
2: sin_data = 8'h8C;
3: sin_data = 8'h92;
4: sin_data = 8'h98;
5: sin_data = 8'h9E;
6: sin_data = 8'hA4;
7: sin_data = 8'hAA;
8: sin_data = 8'hB0;
9: sin_data = 8'hB6;
10: sin_data = 8'hBC;
11: sin_data = 8'hC1;
12: sin_data = 8'hC6;
13: sin_data = 8'hCB;
14: sin_data = 8'hD0;
15: sin_data = 8'hD5;
16: sin_data = 8'hDA;
17: sin_data = 8'hDE;
18: sin_data = 8'hE2;
19: sin_data = 8'hE6;
20: sin_data = 8'hEA;
21: sin_data = 8'hED;
22: sin_data = 8'hF0;
23: sin_data = 8'hF3;
24: sin_data = 8'hF5;
25: sin_data = 8'hF7;
26: sin_data = 8'hF9;
27: sin_data = 8'hFB;
28: sin_data = 8'hFC;
29: sin_data = 8'hFD;
30: sin_data = 8'hFE;
31: sin_data = 8'hFE;
32: sin_data = 8'hFE;
33: sin_data = 8'hFE;
34: sin_data = 8'hFE;
35: sin_data = 8'hFD;
36: sin_data = 8'hFC;
37: sin_data = 8'hFA;
38: sin_data = 8'hF8;
39: sin_data = 8'hF6;
40: sin_data = 8'hF4;
41: sin_data = 8'hF1;
42: sin_data = 8'hEF;
43: sin_data = 8'hEB;
44: sin_data = 8'hE8;
45: sin_data = 8'hE4;
46: sin_data = 8'hE0;
47: sin_data = 8'hDC;
48: sin_data = 8'hD8;
49: sin_data = 8'hD3;
50: sin_data = 8'hCE;
51: sin_data = 8'hC9;
52: sin_data = 8'hC4;
53: sin_data = 8'hBE;
54: sin_data = 8'hB9;
55: sin_data = 8'hB3;
56: sin_data = 8'hAD;
57: sin_data = 8'hA7;
58: sin_data = 8'hA1;
59: sin_data = 8'h9B;
60: sin_data = 8'h95;
61: sin_data = 8'h8F;
62: sin_data = 8'h89;
63: sin_data = 8'h82;
64: sin_data = 8'h7D;
65: sin_data = 8'h77;
66: sin_data = 8'h70;
67: sin_data = 8'h6A;
68: sin_data = 8'h64;
69: sin_data = 8'h5E;
70: sin_data = 8'h58;
71: sin_data = 8'h52;
72: sin_data = 8'h4C;
73: sin_data = 8'h46;
74: sin_data = 8'h41;
75: sin_data = 8'h3C;
76: sin_data = 8'h36;
77: sin_data = 8'h31;
78: sin_data = 8'h2C;
79: sin_data = 8'h28;
80: sin_data = 8'h23;
81: sin_data = 8'h1F;
82: sin_data = 8'h1B;
83: sin_data = 8'h17;
84: sin_data = 8'h14;
85: sin_data = 8'h11;
86: sin_data = 8'hE ;
87: sin_data = 8'hB ;
88: sin_data = 8'h9 ;
89: sin_data = 8'h7 ;
90: sin_data = 8'h5 ;
91: sin_data = 8'h3 ;
92: sin_data = 8'h2 ;
93: sin_data = 8'h1 ;
94: sin_data = 8'h1 ;
95: sin_data = 8'h1 ;
96: sin_data = 8'h1 ;
97: sin_data = 8'h1 ;
98: sin_data = 8'h2 ;
99: sin_data = 8'h3 ;
100: sin_data = 8'h4 ;
101: sin_data = 8'h6 ;
102: sin_data = 8'h7 ;
103: sin_data = 8'hA ;
104: sin_data = 8'hC ;
105: sin_data = 8'hF ;
106: sin_data = 8'h12;
107: sin_data = 8'h15;
108: sin_data = 8'h19;
109: sin_data = 8'h1D;
110: sin_data = 8'h21;
111: sin_data = 8'h25;
112: sin_data = 8'h2A;
113: sin_data = 8'h2E;
114: sin_data = 8'h33;
115: sin_data = 8'h38;
116: sin_data = 8'h3E;
117: sin_data = 8'h43;
118: sin_data = 8'h49;
119: sin_data = 8'h4E;
120: sin_data = 8'h54;
121: sin_data = 8'h5A;
122: sin_data = 8'h60;
123: sin_data = 8'h67;
124: sin_data = 8'h6D;
125: sin_data = 8'h73;
126: sin_data = 8'h79;
127: sin_data = 8'h7F;
endcase
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt1 <= 0;
end
else if(add_cnt1)begin
if(end_cnt1)
cnt1 <= 0;
else
cnt1 <= cnt1 + 1;
end
end
assign add_cnt1 = 1 ;
assign end_cnt1 = 0 ;
always @(*) begin
if(key == 0)begin
x = 262 ;
end
else if(key == 1)begin
x = 524 ;
end
else if(key == 2)begin
x = 786 ;
end
else if(key == 3)begin
x = 1029 ;
end
else if(key == 4)begin
x = 1311 ;
end
else if(key == 5)begin
x = 1573 ;
end
else if(key == 6)begin
x = 1835 ;
end
else begin
x = 2097 ;
end
end
assign addr_temp = cnt1 * x ;
assign addr = addr_temp >> 10 ;
//A通道输出。
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dac_dat_a <= 0 ;
end
else begin
dac_dat_a <= 255 - sin_data ;
end
end
assign dac_sleep = 0 ;
assign dac_mode = 1 ;
assign dac_wra = dac_clka ;
assign dac_clka = ~clk ;
//设计滤波器。
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = 1 ;
assign end_cnt0 = add_cnt0 && cnt0== 4 - 1 ;
assign fir_din = sin_data - 128 ;
ip_fir_1 module_2(
.clk (clk ),
.reset_n (rst_n ),
.ast_sink_data (fir_din ),
.ast_sink_valid (end_cnt0 ),
.ast_sink_error (2'b00 ),
.ast_source_data (fir_dout ),
.ast_source_valid (fir_dout_vld ),
.ast_source_error ( )
);
assign fir_dout2 = fir_dout + 128 ;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dac_dat_b <= 0 ;
end
else if(fir_dout_vld) begin
dac_dat_b <= 255 - fir_dout2 ;
end
end
assign dac_wrb = dac_clkb ;
assign dac_clkb = ~clk ;
endmodule

4、IP核文件 ip_fir_1.v :

`timescale 1 ps / 1 ps
module ip_fir_1 (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
input wire [7:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid
input wire [1:0] ast_sink_error, // .error
output wire [7:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error
);
ip_fir_1_0002 ip_fir_1_inst (
.clk (clk), // clk.clk
.reset_n (reset_n), // rst.reset_n
.ast_sink_data (ast_sink_data), // avalon_streaming_sink.data
.ast_sink_valid (ast_sink_valid), // .valid
.ast_sink_error (ast_sink_error), // .error
.ast_source_data (ast_source_data), // avalon_streaming_source.data
.ast_source_valid (ast_source_valid), // .valid
.ast_source_error (ast_source_error) // .error
);
endmodule

5、测试文件 test_fir.v :

`timescale 1 ns/1 ns
module test_fir();
//时钟和复位
reg clk ;
reg rst_n;
//uut的输入信号
reg[7:0] key ;
//uut的输出信号
wire dac_mode ;
wire dac_sleep ;
wire dac_clka ;
wire [7:0] dac_dat_a ;
wire dac_wra ;
wire dac_clkb ;
wire [7:0] dac_dat_b ;
wire dac_wrb ;
//时钟周期，单位为ns，可在此修改时钟周期。
parameter CYCLE = 200;
//复位时间，此时表示复位3个时钟周期的时间。
parameter RST_TIME = 3 ;
//待测试的模块例化
fir uut(
.clk (clk ),
.rst_n (rst_n ),
.key (key ),
.dac_mode (dac_mode ),
.dac_sleep (dac_sleep ),
.dac_clka (dac_clka ),
.dac_dat_a (dac_dat_a ),
.dac_wra (dac_wra ),
.dac_clkb (dac_clkb ),
.dac_dat_b (dac_dat_b ),
.dac_wrb (dac_wrb )
);
//生成本地时钟50M
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
//产生复位信号
initial begin
rst_n = 1;
#2;
rst_n = 0;
#(CYCLE*RST_TIME);
rst_n = 1;
end
//输入信号key赋值方式
initial begin
forever begin
#(10000*CYCLE);
//赋初值
key = 0;
#(10000*CYCLE);
key = 1;
#(10000*CYCLE);
key = 2;
#(10000*CYCLE);
key = 3;
#(10000*CYCLE);
key = 4;
#(10000*CYCLE);
key = 5;
#(10000*CYCLE);
key = 6;
#(10000*CYCLE);
key = 7;
end
end
endmodule

6、quartus和modelsim联合仿真报错如下图：

恳请各位指正！！

回答 +关注 16

28722人浏览 7人回答问题举报

7 个回答

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zlf1208

本帖最后由 zlf1208 于 2023-8-29 13:38 编辑

awbl 发表于 2023-8-29 07:46
昨天刚pj了IP核，但是还是不行，是不是modelsim还需要**IP核啊。

我搜了一下，请看下面的链接

https://www.intel.cn/content/www/cn/zh/docs/programmable/683463/20-3/generating-ip-simulation-files.html

3598964ed8447142d6.png (134.54 KB )

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2023-08-29

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zlf1208

awbl 发表于 2023-8-29 07:46
昨天刚pj了IP核，但是还是不行，是不是modelsim还需要**IP核啊。

十多年前我用Lattice的器件，用了一个免费的IP核，它在提供IP核的同时，还有一个专门用于仿真的对应IP核的数据文件，我忘记是编译后生成的还是另外提供的了。你可以到ALtera网站去搜一下，看看如何仿真IP核。

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玄德

看提示，提示说了算。

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awbl

FIR.png (271.33 KB )

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2023-8-29 07:45 上传

昨天刚pj了IP核，但是还是不行，是不是modelsim还需要**IP核啊。

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2023-08-29

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zlf1208

IP需要专门的license

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2023-08-28

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玄德

看红字，是不是软件没有 po jie 好？

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2023-08-28

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awbl

自己顶一下

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