日志
Acel FPGA 时序仿真
||
ACTEL的FPGA在做时序仿真的时候，会出现如下错误提示：
# Loading instances from D:/Project/Actel/lib/demo/designer/impl1/counter_ba.sdf
# ** Error: (vsim-SDF-3250) D:/Project/Actel/lib/demo/designer/impl1/counter_ba.sdf(0): Failed to find INSTANCE '/counter_0'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
# Loading proasic3.UFPRB
# Loading proasic3.UDP_MUX2
# ** Error: (vsim-SDF-3250) D:/Project/Actel/lib/demo/designer/impl1/counter_ba.sdf(0): Failed to find INSTANCE '/counter_0'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 15
是因为我们的testbench中例化Module的被例化名称与提示的不样，要么改你例化Module被例化的名称，要么在Start Simulation的SDC标签下更改一下你的apply to region中的名称与你实际例化的一致就可以了
